1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly to a method of fabricating a thin film transistor (TFT) and an array substrate for an LCD device including the TFT.
2. Discussion of the Related Art
As communication technology has developed, a need for compact display devices has developed. Plat panel display devices, such as an LCD device, a plasma display panel (PDP), a vacuum fluorescent display (VFD) device and an organic electroluminescent display (OELD) device, have been developed.
Among these display devices, since the LCD device has a smaller size, lower power consumption than a display device using cathode-ray tubes (CRT), the display device using CRT is replaced by the LCD device. Also, LCD devices are widely used for notebook computers, monitors, TV, and so on, because of their high contrast ratio and characteristics adequate to display moving images.
The LCD device uses optical anisotropy and polarization properties of liquid crystal molecules to display images. The LCD device includes an array substrate including a thin film transistor (TFT) as a switching element and a pixel electrode, a color filter substrate including a color filter layer and a common electrode, and a liquid crystal layer having the liquid crystal molecules. The liquid crystal layer is interposed between the array substrate and the color filter substrate so as to be driven by a vertical electric field induced between the pixel and common electrodes.
Referring to FIGS. 1 and 2, the array substrate is explained.
FIG. 1 is a schematic plan view of an array substrate for an LCD device according to the related art, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1.
In FIG. 1, a gate line 20, a gate electrode 25, an active layer 40, a source electrode 32 and a drain electrode 34, a data line 30, and a pixel electrode 70 are formed on a substrate 10 having a pixel region P. The gate and data lines 20 and 30 cross each other to define the pixel region P. The gate electrode 25 is connected to the gate line 20, and the active layer 40 is formed over the gate electrode 25. The source electrode 32 is connected to the data line 30 and spaced apart from the drain electrode 34. The gate electrode 25, the active layer 40, an ohmic contact layer (not shown), the source electrode 32 and the drain electrode 34 constitute a thin film transistor (TFT) T. Moreover, the pixel electrode 50 is formed in the pixel region “P” to be connected to the drain electrode 34 through a drain contact hole H1. Although not shown, a barrier metal pattern is formed on the ohmic contact layer (not shown) and under the source and drain electrodes 32 and 34.
A method of fabricating an array substrate is explained with FIG. 2. In FIG. 2, the gate electrode 25 is formed on the substrate 10 by depositing and patterning a first metal layer (not shown). At the same time, the gate line 20 (of FIG. 1) is formed from the first metal layer (not shown). Next, an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiO2), is deposited on an entire surface of the substrate 10 including the gate electrode 25 and the gate line 20 (of FIG. 1) to form a gate insulating layer 45.
Next, the active layer 40 and the impurity-doped amorphous silicon layer (not shown) are sequentially formed on the gate insulating layer 45. The active layer 40 and the impurity-doped amorphous silicon layer (not shown) overlap the gate electrode 25. The active layer 40 and the impurity-doped amorphous silicon layer (not shown) may be formed by a plasma enhanced chemical vapor deposition (PECVD). The active layer 40 is formed of intrinsic amorphous silicon, while the impurity-doped amorphous silicon layer (not shown) is formed of impurity-doped amorphous silicon. The ohmic contact layer 41
Next, a barrier metal layer (not shown) and a second metal layer (not shown) are sequentially formed on the ohmic contact layer 41. The barrier metal layer (not shown) is formed of one of titanium (Ti), molybdenum (Mo) and molybdenum-titanium (MoTi) alloy, and the second metal layer (not shown) is formed of copper (Cu). The second metal layer (not shown) is sequentially patterned to form the source and drain electrodes 32 and 34. At the same time, the data line 30 (of FIG. 1) is formed. Next, the barrier metal layer (not shown) and the impurity-doped amorphous silicon layer (not shown) are patterned using the source and drain electrodes 32 and 34 to form a barrier metal pattern 35 and the ohmic contact layer 41. A portion of the active layer 40 is exposed between the ohmic contact layer 41. The exposed portion of the active layer 40 is defined as a channel region. The gate electrode 25, the active layer 40, the ohmic contact layer 41, the source electrode 32 and the drain electrode 34 constitute the thin film transistor (TFT) T.
Next, an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiO2), is deposited to form a passivation layer 55 is foiled on the source and drain electrodes 32 and 34. And then, the passivation layer 55 is patterned to form the drain contact hole H1 exposing a portion of the drain electrode 34.
Next, a pixel electrode 70 of a transparent conductive material is formed on the passivation layer 55 and in the pixel region P. The pixel electrode 70 is connected to the drain electrode 34 through the drain contact hole H1.
In the above-mentioned array substrate, the barrier metal pattern 35 is formed of one of Ti, Mo and MoTi alloy to prevent a Cu material in the source and drain electrodes 32 and 34 being diffused. Since the source and drain electrodes 32 and 34 and the barrier metal pattern 35 are formed of different material, two deposition processes are required. Moreover, since different type etchants should be used, fabricating process becomes complicated.
Furthermore, when a wet-etching process or a photolithography process is performed onto the metal layers, which are formed of dis-similar or different kinds metallic materials, respectively, a problem, such as galvanic corrosion, is caused.
In addition, when a MoTi alloy target is used in a sputtering device, a deposition layer includes a relatively high impurity concentration. Accordingly, the deposition layer has a low adhesive strength to lower or/and upper layers.